1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are driven based on optical anisotropy and polarization characteristics of a liquid crystal material. Liquid crystal molecules have a long and thin shape, and the liquid crystal molecules are regularly arranged along in an alignment direction. Light passes through the LCD device along the long and thin shape of the liquid crystal molecules. The alignment of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment of the liquid crystal molecules changes, and images are displayed. Active matrix liquid crystal display (AMLCD) devices, which include thin film transistors as switching devices for a plurality of pixels, have been widely used due to their high resolution and ability to display fast moving images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer is interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face one another. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field. The direction of the electric field is perpendicular to the substrates. The LCD device has relatively high transmittance and a large aperture ratio. However, the LCD device may have a narrow viewing angle. To increase the viewing angle, various modes have been proposed. Among these wide angle viewing modes, an in-plane switching (IPS) mode LCD device of the related art will be described with reference to accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the IPS mode LCD device according to the related art includes a lower substrate 10 and an upper substrate 40, and a liquid crystal layer LC interposed between the lower substrate 10 and the upper substrate 40. A thin film transistor T, a common electrode 30 and a pixel electrode 32 are formed in each pixel P on the lower substrate 10. The thin film transistor T includes a gate electrode 14, a semiconductor layer 18, and source and drain electrodes 20 and 22. The semiconductor layer 18 is disposed over the gate electrode 14 with a gate insulating layer 16 therebetween. The source and drain electrodes 20 and 22 are formed on the semiconductor layer 18 and are spaced apart from each other. Each of the common electrode 30 and the pixel electrode 32 includes a plurality of patterns. The common electrode 30 and the pixel electrode 32 are spaced apart from and alternate with each other.
Although not shown in FIG. 1, a gate line is formed along a first side of the pixel P, and a data line is formed along a second side of the pixel P substantially perpendicular to the first side. A common line is further formed on the lower substrate 10. The common line provides the common electrode 30 with voltage.
The upper substrate 40 is spaced apart from the lower substrate 10. A black matrix 42 and a color filter layer including red and green color filters 34a and 34b are formed on an inner surface of the upper substrate 40. The color filter layer further includes a blue color filter (not shown). The black matrix 42 is disposed over the gate line, the data line and the thin film transistor T. The color filter layers 34a and 34b are each disposed in a respective pixel P.
The lower substrate 10, including the thin film transistor T, the common electrode 30 and the pixel electrode 32, may be referred to as an array substrate. Liquid crystal molecules of the liquid crystal layer LC are driven by a horizontal electric field 45 induced between the common electrode 30 and the pixel electrode 32. The upper substrate 40, including the black matrix 42 and the color filter layer 34a and 34b, may be referred to as a color filter substrate.
An array substrate for an IPS mode LCD device of the related art will be described with reference to FIG. 2. More specifically, FIG. 2 is a plan view schematically illustrating an array substrate for an IPS mode LCD device manufactured through 4 mask processes according to the related art. As shown in FIG. 2, a gate line 54 is formed along a direction on an insulating substrate 50. A data line 92 crosses the gate line 54 to define a pixel region P. A gate pad 56 is formed at one end of the gate line 54, and a data pad 92 is formed at one end of the data line 92. A common line 58 is spaced apart from and parallel to the gate line 54. The common line 58 is disposed along a side of the pixel region P. A gate pad terminal GP is formed on the gate pad 56 and contacts the gate pad 56. A data pad terminal DP is formed on the data pad 94 and contacts the data pad 94.
A thin film transistor T is formed adjacent to where the gate line 54 crosses the data line 92. The thin film transistor T includes a gate electrode 52, an active layer 84, an ohmic contact layer (not shown), and source and drain electrodes 88 and 90. The gate electrode 52 is connected to the gate line 54. The active layer 84 and the ohmic contact layer are sequentially disposed on the gate electrode 52. The source and drain electrodes 88 and 90 are disposed on the ohmic contact layer. The source electrode 88 is connected to the data line 92. An intrinsic amorphous silicon pattern 72 is disposed under the data line 92. The drain electrode 90 is spaced apart from the source electrode 88.
A pixel electrode PXL and a common electrode Vcom are formed in the pixel region P. The pixel electrode PXL contacts the drain electrode 90, and the common electrode Vcom contacts the common line 58. The pixel electrode PXL and the common electrode Vcom are spaced apart from each other.
In the array substrate for an IPS mode LCD device according to the related art, the source and drain electrodes 88 and 90, the data line 92 and the active layer 84 are formed through the same process. Therefore, the active layer 84 and the source and drain electrodes 88 and 90, and the intrinsic amorphous silicon pattern 72 and the data line 92 are sequentially layered, wherein the active layer 84 and the intrinsic amorphous silicon pattern 72 are exposed at sides of the source and drain electrodes 88 and 90 and the data line 92.
Here, the active layer 84 and the intrinsic amorphous silicon pattern 72 are exposed to light such that photocurrents may occur therein. The photocurrents in the active layer 84 act as leakage currents, which flow when the thin film transistor is OFF, and causes incorrect operation of the thin film transistor T. The photocurrents in the intrinsic amorphous silicon pattern 72 cause coupling with electrodes adjacent thereto, and liquid crystal molecules (not shown) are improperly arranged due to the coupling. Accordingly, a wavy noise occurs on displayed images. The off-currents in the thin film transistor and the appearance of wavy noise in the display typically occur in an LCD device in which the source electrode, drain electrode and the active layer are patterned through the same process.
FIGS. 3A to 3H, FIGS. 4A to 4H, FIGS. 5A to 5H, and FIGS. 6A to 6H illustrate processes of manufacturing an array substrate for an IPS mode LCD device according to the related art. FIGS. 3A to 3H are cross-sectional views along the line II-II of FIG. 2. FIGS. 4A to 4H are cross-sectional views along the line III-III of FIG. 2. FIGS. 5A to 5H are cross-sectional views along the line IV-IV of FIG. 2. FIGS. 6A to 6H are cross-sectional views along the line V-V of FIG. 2.
FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A show a first mask process. As shown in FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A, a switching region S, a pixel region P, a gate region G, a data region D, and a common signal region CS are defined on a substrate 50. A gate line 54 of FIG. 2 and a gate electrode 50 are formed on the substrate 50 including the regions S, P, G, D and CS. The gate line 54 is disposed in the gate region G and extends along a first direction. The gate line 54 includes a gate pad 56 at one end thereof. The gate electrode 52 is connected to the gate line 54 and is disposed in the switching region S. Simultaneously, a common line 58 is formed in the common signal region CS. The common line 58 is spaced apart from and parallel to the gate line 54.
The gate line 54, the gate pad 56, the gate electrode 52 and the common line 58 are formed by depositing one or more material selected from a conductive metallic group including aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo). The gate line 54, the gate pad 56, the gate electrode 52 and the common line 58 may be a single layer of the above-mentioned metallic material or may be a double layer of aluminum (Al)/chromium (Cr) or aluminum (Al)/molybdenum (Mo).
FIGS. 3B to 3F, FIGS. 4B to 4F, FIGS. 5B to 5F and FIGS. 6B to 6F show a second mask process. As shown in FIG. 3B, FIG. 4B, FIG. 5B and FIG. 6B, a gate insulating layer 60, an intrinsic amorphous silicon layer (a-Si:H) 62, an impurity-doped amorphous silicon layer (n+ or p+ a-Si:H) 64, and a conductive metallic layer 66 are formed over the entire surface of the substrate 50, including the gate line 54, the gate pad 56, the gate electrode 52 and the common line 58. The gate insulating layer 60 is formed by depositing one or more material selected from an inorganic insulating material group, including silicon nitride (SiNx) and silicon oxide (SiO2). The conductive metallic layer 66 is formed by depositing one or more material selected from the above-mentioned conductive metallic group.
A photoresist layer 68 is formed by coating the entire surface of the substrate 50, including the conductive metallic layer 66 with photoresist. A mask M is disposed over the photoresist layer 68. The mask M includes a light-transmitting portion B1, a light-blocking portion B2, and a light-half transmitting portion B3. The light-transmitting portion B1 transmits substantially all light. The photoresist layer 68 below the light-transmitting portion B1 is entirely exposed to light to thereby chemically change. The light-blocking portion B2 completely blocks the light. The light-half transmitting portion B3 includes slits or a half transparent layer to decrease the intensity of light or transmittance of the light. Thus, the photoresist layer is partially exposed to light through the light-half transmitting portion B3.
The light-half transmitting portion B3 is disposed over the gate electrode 52 in the switching region S. The light-blocking portion B2 is disposed over the photoresist layer 68 in the switching region S and in the data region D. In the switching region S, the light-blocking portion B2 is disposed at both sides of the light-half transmitting portion B3. The light-transmitting portion B1 is disposed in other regions except form the switching region S and the data region D. The photoresist layer 68 is exposed to light through the mask M and then is developed.
Referring to FIG. 3C, FIG. 4C, FIG. 5C and FIG. 6C, first and second photoresist patterns 70a and 70b are formed in the switching region S and the data region D, respectively. The first photoresist pattern 70a has a first portion corresponding to the gate electrode 52 and a second portion corresponding to the switching region S except form the gate electrode 52. The second portion is thicker than the first portion.
Next, the conductive metallic layer 66, the impurity-doped amorphous silicon layer 64, and the intrinsic amorphous silicon layer 62 are selectively removed by using the first and second photoresist patterns 70a and 70b as an etching mask. The conductive metallic layer 66 may be removed simultaneously with the under layers 64 and 62 according to a material of the conductive metallic layer 66. Alternatively, the conductive metallic layer 66 may be wet-etched. Then, the impurity-doped amorphous silicon layer 64 and the intrinsic amorphous silicon layer 62 may be dry-etched.
As shown in FIG. 3D, FIG. 4D, FIG. 5D and FIG. 6D, a first metallic pattern 78 and a second metallic pattern 82 are formed under the first and second photoresist patterns 70a and 70b, respectively. A first semiconductor pattern 76 and a second semiconductor pattern 80 are formed under the first metallic pattern 78 and the second metallic pattern 82, respectively. Each of the first and second semiconductor patterns 76 and 80 includes an intrinsic amorphous silicon pattern 72 and an impurity-doped amorphous silicon pattern 74.
As shown in FIG. 3E, FIG. 4E, FIG. 5E and FIG. 6E, an ashing process is performed to remove a first portion of the first photoresist pattern 70a corresponding to the gate electrode 52, and the first metallic pattern 78 corresponding to the gate electrode 52 is exposed. At this time, other parts of the first photoresist pattern 70a and the second photoresist pattern 70b are also partially removed. The first and second metallic patterns 78 and 82 are partially exposed at peripheries of the first and second photoresist patterns 70a and 70b. Then, the exposed first metallic pattern 78 and the impurity-doped amorphous silicon pattern 74 of the first semiconductor layer 76 are removed.
Referring to FIG. 3F, FIG. 4F, FIG. 5F and FIG. 6F, a source electrode 88, a drain electrode 90 and a data line 92 are formed. The data line 92 is formed in a second direction crossing the first direction. A data pad 94 is formed at one end of the data line 92. The intrinsic amorphous silicon pattern 72 of the first semiconductor pattern 76 of FIG. 3E over the gate electrode 52 functions as an active layer 84, and the impurity-doped amorphous silicon pattern 74 of the first semiconductor pattern 76 of FIG. 3E, which is now divided into two parts, acts as an ohmic contact layer 86. When the impurity-doped amorphous silicon pattern 74 of the first semiconductor pattern 76 of FIG. 3E is partially removed, the intrinsic amorphous silicon pattern, i.e., the active layer 84, is over-etched so that particles may not remain on the surface of the active layer 84. Next, the photoresist patterns 70a and 70b are removed.
FIG. 3G, FIG. 4G, FIG. 5G and FIG. 6G show a third mask process. As shown in FIG. 3G, FIG. 4G, FIG. 5G and FIG. 6G, a passivation layer 96 is formed substantially over an entire surface of the substrate 50, including the source and drain electrodes 88 and 90 and the data line 92 including the data pad 94. The passivation layer 96 may be formed by depositing one selected from an inorganic insulating material group, including silicon nitride (SiNx) and silicon oxide (SiO2). Alternatively, the passivation layer 96 may be formed by coating the substrate 50 with one selected from an organic insulating material group, including benzocyclobutene (BCB) and acrylic resin.
Subsequently, the passivation layer 96 is patterned to thereby form a drain contact hole 98a, a common line contact hole 98b, a gate pad contact hole 98c, and a data pad contact hole 98d. The drain contact hole 98a partially exposes the drain electrode 90. The common line contact hole 98b partially exposes the common line 58. The gate pad contact hole 98c partially exposes the gate pad 56. The data pad contact hole 98d partially exposes the data pad 94.
FIG. 3H, FIG. 4H, FIG. 5H and FIG. 6H show a fourth mask process. As shown in FIG. 3H, FIG. 4H, FIG. 5H and FIG. 6H, a pixel electrode PXL and a common electrode Vcom are formed in the pixel region P by depositing one selected from a transparent conductive metallic group, including indium tin oxide (ITO) and indium zinc oxide (IZO), on the substrate 650 including the passivation layer 96, and then patterning it. The pixel electrode PXL contacts the drain electrode 90, and the common electrode Vcom contacts the common line 58. Each of the pixel electrode PXL and the common electrode Vcom includes a plurality patterns parallel to the data line 92. The common electrode Vcom alternates with the pixel electrode PXL. A gate pad terminal GP and a data pad terminal DP are formed simultaneously with the pixel electrode PXL and the common electrode Vcom. The gate pad terminal GP contacts the gate pad 56. The data pad terminal DP contacts the data pad 94.
The array substrate for an IPS mode LCD device may be manufactured through the above-mentioned four mask processes. Since the active layer and the source and drain electrodes are formed through the same process, the manufacturing costs and time can be reduced. The probability that problems may occur also decreases. However, in the array substrate manufactured through four mask processes, the second semiconductor pattern 80 is formed under the data line 92, and the intrinsic amorphous silicon pattern 72 of the second semiconductor pattern 80 is exposed at sides of the data line 92. As stated above, the exposed intrinsic amorphous silicon pattern 72 is affected by light and causes wavy noise in images that are displayed. In addition, the active layer 84 also goes beyond the gate electrode 52 and is exposed to light. Thus, photocurrents in the active layer 84 occur which cause the thin film transistor works incorrectly.